1. Field of the Invention
The present invention relates to a semiconductor device configured to control a connection between a sense amplifier connected to a bit line and an input/output line using a column select line.
2. Description of Related Art
In general, a semiconductor memory such as a DRAM is provided with sense amplifiers that sense and amplify signals read out from selected memory cells through bit lines and is configured to transfer output signals from the sense amplifiers through hierarchical input/output lines. In the semiconductor memory, control is usually performed so as to select a sense amplifier from a plurality of sense amplifiers based on a column select signal supplied to a column select line and to connect the selected sense amplifier to an input/output line. However, it is required to arrange one column select line for each several sense amplifiers, and therefore this causes an increase in the number of column select lines with an increase in capacity of the semiconductor memory. As measures against this, a method has been proposed in which lines of select signals are arranged separately from the column select lines and the sense amplifier is selected based on the column select lines and the lines of select signals (for example, refer to Patent References 1 to 6). For example, FIG. 7 of Patent Reference 5 discloses a configuration in which connection of sense amplifiers (SA0 to SA3) to a common IO line (e.g., IO0) is switched by using column select signals (YS0 and YS1) and column bank select signal lines (CBS0 and CBS1). Also, for example, FIG. 2 of Patent Reference 6 discloses a configuration in which one global column select switch (10) is arranged between one column select line (7) and four local column select switches (20).    [Patent Reference 1] Japanese Patent Application Laid-open No. 2000-322883    [Patent Reference 2] Japanese Patent Application Laid-open No. H8-279290 (U.S. Pat. No. 5,764,562)    [Patent Reference 3] Japanese Patent Application Laid-open No. 2000-331474 (U.S. Pat. No. 6,259,641)    [Patent Reference 4] Japanese Patent Application Laid-open No. 2002-230968 (U.S. Pat. No. 6,404,695)    [Patent Reference 5] Japanese Patent Application Laid-open No. H11-306755    [Patent Reference 6] Japanese Patent Application Laid-open No. 2006-134469 (U.S. Pat. No. 7,180,817)
In semiconductor memory devices of recent years such as a DRAM, miniaturization of elements such as wiring lines has been developed from viewpoints of a reduction in chip area and a reduction in power consumption. However, if linewidths are reduced due to the miniaturization, wiring resistance thereof becomes large. For example, if the wiring resistance of a power supply line becomes large, the potential of a supply voltage supplied to elements of the semiconductor memory through the power supply line falls. In the semiconductor memory, for example, power supply lines supplied to amplifiers such as sense amplifiers are generally arranged over a memory array including a plurality of memory cells, and therefore if the potential of the supply voltage supplied through the power supply lines falls, an operation of the semiconductor memory becomes unstable. In order to suppress the reduction of the supply voltage, the resistance of the power supply lines needs to be reduced by increasing the number of power supply lines. However, the number of wiring lines that can be arranged in a wiring layer of a general semiconductor memory is physically restricted by an area of the wiring layer. Accordingly, in order to increase the number of power supply lines, as described above, it is required that a new wiring layer is added or that the number of other lines (e.g., signal lines) arranged in the same wiring layer as for the power supply lines is reduced. Even if the number of power supply lines is increased by adding the wiring layer, there is a problem that manufacturing cost of the semiconductor memory increases.
The configuration disclosed in Patent Reference 5 (FIG. 7 of the Patent Reference 5) is capable of reducing the number of column select lines in comparison with the conventional configuration shown in the Patent Reference 5 (FIG. 8 of the Patent Reference 5), and thus the number of power supply lines arranged in the same layer as for the column select lines can be reduced. However, the configuration disclosed in the Patent Reference 5 requires at least two transistors (SY and SC) between the sense amplifier (SA) and the input/output line (IO), and therefore there is a problem that the operating speed of the semiconductor memory is reduced.
Meanwhile, the configuration disclosed in Patent Reference 2 that enables speeding-up the column select operation is not capable of reducing the number of column select lines, and thus the above problem of the reduction of the supply voltage has not been solved.